PLL使用出错

2019-03-25 07:37发布

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求指教，Error: Clock input port inclk[0] of PLL "pll:inst243|altpll:altpll_component|pll" must be driven by a non-inverted input pin or another PLL, optionally through a Clock Control block
        Info: Input port INCLK[0] of node "pll:inst243|altpll:altpll_component|pll" is driven by cic:inst170|clkout which is REGOUT output port of Register cell type node cic:inst170|clkout
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5525
2019-03-26 07:13
时钟，重要性不多说。

Error: Clock input port inclk[0] of PLL "pll2:inst73|altpll:altpll_component|pll" must be driven by a non-inverted input pin or another PLL, optionally through a Clock Control block        
1.说时钟要直接从pin过来，没有必要取反。
2.说PLL的输入可以是其他PLL的输出，

Info: Input port INCLK[0] of node "pll2:inst73|altpll:altpll_component|pll" is driven by clkopt:inst57|Mux0 which is COMBOUT output port of Combinational cell type node clkopt:inst57|Mux0
1.说时钟的输入不能是组合逻辑

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