STM32

开贴记录SWD 脱机烧录器开发过程，请各路大神指教

2019-12-09 19:23发布

站内问答 / STM32/STM8
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参考 CMISI_DAP,BlackMagic代码。
预备下周末结案，目前方案：
1：Host用STM32F427，跑RTEMS系统， IO口模拟SWD时序。
2：flash的操作函数，由Host通过SWD下载入target ram执行。（CMISI_DAP采用这种方式）
     不知道jlink的flash操作是不是一样的原理。他要适用这么多芯片，那得有准备多少这样的小程序啊。。。
3：USB用的虚拟串口，用ST官方提供的驱动，上位机编程简单。tafget本身程序.bin文件由上位机通过虚拟串口传入。
     此虚拟串口的波特率，奇偶，起停位设置均形同虚设。

目前状态：
SWD时序基本调试通过，读写target ID/reg已经正常，暂时未经过高强度测试。。
正在弄flash操作。
友情提示: 此问题已得到解决，问题已经关闭,关闭后问题禁止继续编辑，回答。
94条回答
shangdawei
2019-12-13 09:32
swddude -- A SWD programmer for ARM Cortex microcontrollers.

需要提供底层驱动

swddude-master.zip (55.88 KB, 下载次数: 107) 2015-8-22 21:18 上传 点击文件名下载附件



  1. #ifndef SWD_H
  2. #define SWD_H

  4. /*
  5. * Abstract base class for SWD interface drivers.
  6. */

  8. #include "libs/error/error_stack.h"

  10. #include <stdint.h>

  12. /*
  13. * SWDDriver provides a low-level interface to SWD interface devices.
  14. * Each function maps directly to a SWD protocol concept.  The ARM ADIv5
  15. * specification explains the SWD protocol in more detail; it's available
  16. * behind a clickwrap license on ARM's site.
  17. *
  18. * Client software should rarely interact with SWDDriver directly.  Instead,
  19. * wrap it in another object that provides a higher-level more pleasant
  20. * interface with support for things like retries and named registers.
  21. */
  22. class SWDDriver {
  23. public:
  24.     /*
  25.      * Creates an instance of the driver.  Because the constructor can't
  26.      * return any meaningful error condition, implementations should only do
  27.      * things that can't fail -- such as copying in constructor arguments
  28.      * and initializing memory.
  29.      */
  30.     SWDDriver() {}

  32.     /*
  33.      * Destroys this driver instance.  Because the destructor can't return
  34.      * any meaningful error condition, any resource cleanup here is
  35.      * last-resort.  Clients should call the close() function to clean up
  36.      * resources in a way that can report errors.  Destructor
  37.      * implementations may optionally log attempts to destroy a driver
  38.      * instance without calling close(), as this indicates a programming
  39.      * error.
  40.      */
  41.     virtual ~SWDDriver() {}

  43.     /*
  44.      * Initialize the SWD link to the target, per the "Connection and line
  45.      * reset sequence" defined by the ARM ADI v5.  This has two parts:
  46.      *   1. 50 clocks with the SWDIO line held high by the master.
  47.      *   2. A read of the IDCODE register in the DP.
  48.      *
  49.      * Because this function reads IDCODE behind the scenes, it can
  50.      * optionally return it to the application through the pointer argument.
  51.      *
  52.      * If this function returns successfully, it indicates that the
  53.      * interface is functioning, and that an attached microprocessor has
  54.      * responded to us.  The state of the target is unknown -- in
  55.      * particular, the contents of the Debug Access Port's SELECT and
  56.      * CTRL/STAT registers are undefined.
  57.      *
  58.      * Return values:
  59.      *  Err::success - initialization complete, target responded, IDCODE
  60.      *                 valid.
  61.      *  Err::failure - initialization failed or target failed to respond.
  62.      */
  63.     virtual Err::Error initialize(uint32_t * idcode_out = 0) = 0;

  65.     /*
  66.      * Asserts the target's reset line continuously until a call to
  67.      * leave_reset.
  68.      *
  69.      * Return values:
  70.      *  Err::success - reset asserted.
  71.      *  Err::failure - communications with interface failed.
  72.      */
  73.     virtual Err::Error enter_reset() = 0;

  75.     /*
  76.      * Deasserts the target's reset line, allowing it to run.
  77.      *
  78.      * Return values:
  79.      *  Err::success - reset deasserted.
  80.      *  Err::failure - communications with interface failed.
  81.      */
  82.     virtual Err::Error leave_reset() = 0;

  84.     /*
  85.      * Reads a 32-bit register from either the Debug Access Port (when
  86.      * debug_port is true) or the Access Port bank named in the DAP's SELECT
  87.      * register (when debug_port is false).
  88.      *
  89.      * Access Port reads are delayed: each read returns the result of the
  90.      * previous operation.  To kick off a read without retrieving the
  91.      * results of the last one, pass a data pointer of zero; the result
  92.      * won't be written.  To retrieve the results of the last Access Port
  93.      * read without starting a new one, read the Debug Access Port's RDBUFF
  94.      * register instead.  
  95.      *
  96.      * Note that some registers can only be accessed in particular states of
  97.      * the CTRL/STAT register, and some registers can't be read at all.
  98.      *
  99.      * Refer to the ARM ADIv5 spec for more information.
  100.      *
  101.      * Implementation note: drivers should implement this function such that
  102.      * it will work regardless of mode.  In particular, it must not assume
  103.      * that Overrun Detection is enabled in the DAP.
  104.      *
  105.      * Return values:
  106.      *  Err::success   - read completed, data valid.
  107.      *  Err::try_again - target returned SWD WAIT response, read not
  108.      *                   completed.
  109.      *  Err::failure   - read failed, either in the interface or due to SWD
  110.      *                   FAULT.
  111.      */
  112.     virtual Err::Error read(unsigned   address,
  113.                             bool       debug_port,
  114.                             uint32_t * data) = 0;

  116.     /*
  117.      * Writes a 32-bit value into a register in either the Debug Access Port
  118.      * (when debug_port is true) or the Access Port bank named in the DAP's
  119.      * SELECT register (when debug_port is false).
  120.      *
  121.      * Access Port writes may take time to complete.  For a MEM-AP, monitor
  122.      * the status of the TrInProg (transaction in progress) bit of the
  123.      * Access Port's CSW register to detect when another write may be
  124.      * issued.
  125.      *
  126.      * Note that some registers can only be accessed in particular states of
  127.      * the CTRL/STAT register, and some registers can't be written at all.
  128.      *
  129.      * Refer to the ARM ADIv5 spec for more information.
  130.      *
  131.      * Implementation note: drivers should implement this function such that
  132.      * it will work regardless of mode.  In particular, it must not assume
  133.      * that Overrun Detection is enabled in the DAP.
  134.      *
  135.      * Return values:
  136.      *  Err::success   - write completed.
  137.      *  Err::try_again - target returned SWD WAIT response, write not
  138.      *                   completed.
  139.      *  Err::failure   - write failed, either in the interface or due to SWD
  140.      *                   FAULT.
  141.      */
  142.     virtual Err::Error write(unsigned address,
  143.                              bool     debug_port,
  144.                              uint32_t data) = 0;
  145. };

  147. #endif  // SWD_H
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