FPGA中用VHDL语言写BH1750光敏模块的显示，一直无法驱动BH1750，求大神帮助-efans

FPGA中用VHDL语言写BH1750光敏模块的显示，一直无法驱动BH1750，求大神帮助

2019-07-15 22:13发布

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity adc is
Port ( adc_out : out  STD_LOGIC_vector(15 downto 0);
         SCL : out  STD_LOGIC;
         SDA : inout  STD_LOGIC;
         clk50MHz : in  STD_LOGIC;
         adc_en : in  STD_LOGIC);
end adc;

architecture Behavioral of adc is

constant slaveaddress2 :std_logic_vector(7 downto 0) := x"47";
constant h_resolution_mode :std_logic_vector(7 downto 0) := x"10";
constant poweron : std_logic_vector(7 downto 0) := x"01";
signal delay5us : std_logic_vector(7 downto 0);
type state is (step1,step2,step3,step4,step5,step6,step7,step8,step9,step10,step11,step12,step13,step14,
step15,step16,step17,step18,step19,step20,step21,step22,step23,step24,step25,step26,step27,step28,step29,step30,
step31,step32,step33,step34,step35,step36,step37,step38,step39,step40,step42,step43,step44,step45,step46,step47);
type state_send is(a1,a2,a3,a4);
signal state2 : state_send ;
signal state1 : state;
signal counter : integer range 0 to 7;
constant slaveaddress : std_logic_vector(7 downto 0):=x"46";
signal delay180ms : std_logic_vector(23 downto 0);
type state_receive is (b1,b2,b3,b4,b5);
signal state3 :state_receive ;
signal counter2 : integer range 8 to 15;
signal temp : std_logic_vector(15 downto 0);
signal delay5ms :std_logic_vector(7 downto 0);
signal counter3 :integer range 0 to 7;

begin

process(clk50MHz,adc_en)
begin
if adc_en='1' then
if clk50MHz' event and clk50MHz='1' then
case state1 is
when step1 => ---------start-------------
SDA<='1';
SCL<='1';
state1<=step2;
when step2 => -----------delay-----------------
if delay5us=x"FA" then
state1<=step3;
delay5us<=x"00";
else
delay5us<=delay5us+1;
end if;------------------------------------------
when step3 =>
SDA<= '0';
state1 <=step4;
when step4 =>
if delay5us=x"FA" then
state1<=step5;
delay5us<=x"00";
else
delay5us<=delay5us+1;
end if;
when step5 =>
SCL<='0';
state1<=step6; -----------over--------------------
when step6 =>
case state2 is
when a1 =>
SDA<=slaveaddress(counter);
SCL<='1';
state2<=a2;
when a2 =>
if delay5us=x"FA" then
state2<=a3;
delay5us<=x"00";
else
delay5us<=delay5us+1;
end if;
when a3 =>
SCL<='0';
state2<=a4;
when a4=>
if delay5us=x"FA" then
if counter = 0 then
state1<=step7;
counter<=7;
state2<=a1;
delay5us<=x"00";
else
counter<=counter-1;
state2<=a1;
delay5us<=x"00";
end if;
else
delay5us<=delay5us+1;
end if;
end case;
when step7 =>
case state2 is
when a1 =>
SDA<=poweron(counter);
SCL<='1';
state2<=a2;
when a2 =>
if delay5us=x"FA" then
state2<=a3;
delay5us<=x"00";
else
delay5us<=delay5us+1;
end if;
when a3 =>
SCL<='0';
state2<=a4;
when a4=>
if delay5us=x"FA" then
if counter=0 then
state1<= step8;
counter<=7;
state2<=a1;
delay5us<=x"00";
else
counter<=counter-1;
state2<=a1;
delay5us<=x"00";
end if;
else
delay5us<=delay5us+1;
end if;
end case;
when step8 =>    ---------------stop----------------------
SDA<='0';
SCL<='1';
state1<=step9;
when step9 =>
if delay5us=x"FA" then
state1<=step10;
delay5us<=x"00";
else
delay5us<=delay5us+1;
end if;
when step10 =>
SDA<='1';
state1<=step11;
when step11 =>
if delay5us=x"FA" then
state1<=step12;
delay5us<=x"00";
else
delay5us<=delay5us+1;
end if;       -----------------over------------------------
when step12 =>
SDA<='1';
SCL<='1';
state1<=step13;
when step13 =>
if delay5us=x"FA" then
state1<=step14;
delay5us<=x"00";
else
delay5us<=delay5us+1;
end if;
when step14 =>
SDA<= '0';
state1 <=step15;
when step15 =>
if delay5us=x"FA" then
state1<=step16;
delay5us<=x"00";
else
delay5us<=delay5us+1;
end if;
when step16 =>
SCL<='0';
state1<=step17;
when step17 =>
case state2 is
when a1 =>
SDA<=slaveaddress(counter);
SCL<='1';
state2<=a2;
when a2 =>
if delay5us=x"FA" then
state2<=a3;
delay5us<=x"00";
else
delay5us<=delay5us+1;
end if;
when a3 =>
SCL<='0';
state2<=a4;
when a4=>
if delay5us=x"FA" then
if counter = 0 then
state1<= step18;
counter<=7;
state2<=a1;
delay5us<=x"00";
else
counter<=counter-1;
state2<=a1;
delay5us<=x"00";
end if;
else
delay5us<=delay5us+1;
end if;
end case;
when step18 =>
case state2 is
when a1 =>
SDA<=h_resolution_mode(counter);
SCL<='1';
state2<=a2;
when a2 =>
if delay5us=x"FA" then
state2<=a3;
delay5us<=x"00";
else
delay5us<=delay5us+1;
end if;
when a3 =>
SCL<='0';
state2<=a4;
when a4=>
if delay5us=x"FA" then
if counter=0 then
state1<= step19;
counter<=7;
state2<=a1;
delay5us<=x"00";
else
counter<=counter-1;
state2<=a1;
delay5us<=x"00";
end if;
else
delay5us<=delay5us+1;
end if;
end case;
when step19 =>
SDA<='0';
SCL<='1';
state1<=step20;
when step20 =>
if delay5us=x"FA" then
state1<=step21;
delay5us<=x"00";
else
delay5us<=delay5us+1;
end if;
when step21 =>
SDA<='1';
state1<=step22;
when step22 =>
if delay5us=x"FA" then
state1<=step23;
delay5us<=x"00";
else
delay5us<=delay5us+1;
end if;
when step23 =>
if delay180ms=x"895440" then
state1<=step24;
delay180ms<=x"000000";
else
delay180ms<=delay180ms+1;
end if;
when step24 => ---------start-----------------------
SDA<='1';
SCL<='1';
state1<=step25;
when step25 =>
if delay5us=x"FA" then
state1<=step26;
delay5us<=x"00";
else
delay5us<=delay5us+1;
end if;
when step26 =>
SDA<= '0';
state1 <=step27;
when step27 =>
if delay5us=x"FA" then
state1<=step28;
delay5us<=x"00";
else
delay5us<=delay5us+1;
end if;
when step28 =>
SCL<='0';
state1<=step29; -----------over-----------------
when step29 =>
case state2 is
when a1 =>
SDA<=slaveaddress2(counter);
SCL<='1';
state2<=a2;
when a2 =>
if delay5us=x"FA" then
state2<=a3;
delay5us<=x"00";
else
delay5us<=delay5us+1;
end if;
when a3 =>
SCL<='0';
state2<=a4;
when a4=>
if delay5us=x"FA" then
if counter=0 then
state1<= step30;
counter<=7;
state2<=a1;
delay5us<=x"00";
else
counter<=counter-1;
state2<=a1;
delay5us<=x"00";
end if;
else
delay5us<=delay5us+1;
end if;
end case;

when step30 =>    ------------------receive h data------------------------
SDA<='1';
state1<=step31;
when step31 =>
case state3 is
when b1 =>
SCL<='1';
state3<=b2;
when b2 =>
if delay5us=x"FA" then
state3<=b3;
delay5us<=x"00";
else
delay5us<=delay5us+1;
end if;
when b3 =>
temp(counter2)<=SDA;
state3<=b4;
when b4 =>
SCL<='0';
state3<=b5;
when b5 =>
if delay5us=x"FA" then
if counter2=8 then
state1<=step42;
counter2<=15;
delay5us<=x"00";
state3<=b1;
else
state3<=b1;
counter2<=counter2-1;
delay5us<=x"00";
end if;
else
delay5us<=delay5us+1;
end if;
end case;
when step42 =>       ----------------Ack=0------------------------------
SDA<='0';
SCL<='1';
state1<=step43;
when step43 =>
if delay5us=x"FA" then
state1<=step44;
delay5us<=x"00";
else
delay5us<=delay5us+1;
end if;
when step44 =>
SCL<='0';
state1<=step45;
when step45 =>
if delay5us=x"FA" then
state1<=step46;
delay5us<=x"00";
else
delay5us<=delay5us+1;
end if;
when step46 =>             -------------receive  low data----------------
SDA<='1';
state1<=step47;
when step47 =>
case state3 is
when b1 =>
SCL<='1';
state3<=b2;
when b2 =>
if delay5us=x"FA" then

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2条回答

efans_7c4

2019-07-15 23:37

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