library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity xuanze is
port( s,c:in integer range 0000 to 9999;
      s1,s2,s3,s4,c1,c2,c3,c4:buffer integer range 0 to 9);
end;      
architecture one of xuanze is
   signal a1,a2,a3,a4,b1,b2,b3,b4:integer:=0;
   
    signal a:integer:=s;
    signal b:integer:=c;
begin
    process(a,b)
    begin   
    if(a>999 and a<=9999) then a<=a-1000;a1<=a1+1;s1<=a1;
    elsif(a>99 and a<=999) then a<=a-100;a2<=a2+1;s2<=a2;
    elsif(a>9 and a<=99) then a<=a-10;a3<=a3+1;s3<=a3;
     else a<=a-1; a4<=a4+1;s4<=a4;
     end if;
     if(b>999 and b<=9999) then b<=b-1000;b1<=b1+1;c1<=b1;
    elsif(b>99 and b<=999) then b<=b-100;b2<=b2+1;c2<=b2;
    elsif(b>9and b<=99) then b<=b-10;b3<=b3+1;c3<=b3;
     else b<=b-1;b4<=b4+1;c4<=b4;
end if;
   end process;
   end one;
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