本帖最后由 elecfans跑堂 于 2015-9-6 13:49 编辑
源代码:`
timescale 1ns / 1psmodule led_key(clk,key1,key2,led,rst_n
);
input clk;
input rst_n;
input key1,key2; //key1控制流水灯左移,key2--右移
output [7:0]led;
reg key1_r;
reg key2_r;
reg [1:0]led_dir;
reg [7:0]led_r;
//=======================
always@(posedge clk or posedge rst_n)begin
if(rst_n)begin
key1_r <= 1'b0;
key2_r <= 1'b0;
end
else begin
key1_r <= key1;
key2_r <= key2;
end
end
//==计数器做延时
reg [15:0]cnt;
always@(posedge clk or posedge rst_n)begin
if(rst_n) cnt <= 16'b0;
else cnt <= cnt + 1'b1;
end
//== 读按键的状态
always@(posedge clk )begin
led_dir <= {key2_r,key1_r};
case(led_dir)
2'b00: led_r <= 8'b0000_0000; //都不亮
2'b01: begin
led_r <= 8'b0000_0001; //led左移
if(cnt == 16'b1000_0000_0000_0000) led_r <= {led_r[6:0],led_r[7]};
end
2'b10: begin
led_r <= 8'b1000_0000; //led右移
if(cnt == 16'b1000_0000_0000_0000) led_r <= {led_r[0],led_r[7:1]};
end
2'b11: led_r <= 8'b1111_1111; //全亮
endcase
end
assign led = led_r;
endmodule
感觉每次都进不了if(cnt == 16'b1000_0000_0000_0000)语句,不知为什么?求大神解答?
语句每个时钟点都对赋值 led_r <= 8'b0000_0001; //led左移
这条语句(if(cnt == 16'b1000_0000_0000_0000) led_r <= {led_r[6:0],led_r[7]};)执行完后,LED数据改变,但下次再进入CASE语句时,语句:led_r <= 8'b0000_0001; 又将其改写为了8'b0000_0001,而if(cnt == 16'b1000_0000_0000_0000) 条件不再满足,后续语句不再更新LED,所以led_r只会出现8'b0000_0001, 和8'b0000_0010,且停留在8'b0000_0010时间非常短(一个时钟周期),当频率太快时,基本看不到现象。
一周热门 更多>